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Description: This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
Platform: |
Size: 114780 |
Author: king.xia |
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Description: RAM（Random Access Memory）随机存取存储器对于系统性能的影响是每个PC用户都非常清楚的，所以很多朋友趁着现在的内存价格很低纷纷扩容了内存，希望借此来得到更高的性能。不过现在市场是多种内存类型并存的，SDRAM、DDR SDRAM、RDRAM等等，如果你使用的还是非常古老的系统，可能还需要EDO DRAM、FP DRAM（块页）等现在不是很常见的内存-RAM (Random Access Memory) random access memory system performance for the impact of each PC users are very clear, so many of my friends now take advantage of the low prices have memory expansion memory, with a view to get higher performance. But now the market is a mixture of both types of memory, SDRAM, DDR SDRAM, RDRAM, etc. If you use or the very old, may also need to EDO DRAM, FP DRAM (block pages) is now is not very common memory
Platform: |
Size: 775168 |
Author: 周卫成 |
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Description: RAM（Random Access Memory）随机存取存储器对于系统性能的影响是每个PC用户都非常清楚的，所以很多朋友趁着现在的内存价格很低纷纷扩容了内存，希望借此来得到更高的性能。不过现在市场是多种内存类型并存的，SDRAM、DDR SDRAM、RDRAM等等，如果你使用的还是非常古老的系统，可能还需要EDO DRAM、FP DRAM（块页）等现在不是很常见的内存-RAM (Random Access Memory) random access memory system performance for the impact of each PC users are very clear, so many of my friends now take advantage of the low prices have memory expansion memory, with a view to get higher performance. But now the market is a mixture of both types of memory, SDRAM, DDR SDRAM, RDRAM, etc. If you use or the very old, may also need to EDO DRAM, FP DRAM (block pages) is now is not very common memory
Platform: |
Size: 1052672 |
Author: 周卫成 |
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Description: 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and high-speed data acquisition, and so on the embedded system, Cache require large amounts of data. DDR (Double Data Rate, double-data rate) SDRAM due to its speed, large capacity, and their prices are cheaper, it can be a very good occasion to meet these massive data cache demand. But DDR SDRAM interface directly with today's microprocessor and DSP memory interface connected, During the need to insert controller microprocessor or DSP memory of the control.
Platform: |
Size: 237568 |
Author: joucan |
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Description: ddr and sdram memory check,ddr and sdram memory check-ddr sdram memory and check, ddr sdram memory check and
Platform: |
Size: 136192 |
Author: wangdong |
Hits:
Description: This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
Platform: |
Size: 114688 |
Author: |
Hits:
Description: ddr verilog代码,实现DDR内存控制，是一个高效率的程序-ddr verilog code, realize DDR memory control, is a highly efficient procedure
Platform: |
Size: 38912 |
Author: |
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Description: nois中基于c的ddr等存储器的checksum的实现.-nois-based c of ddr memory, such as the realization of the checksum.
Platform: |
Size: 6144 |
Author: qiuxin_88 |
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Description: 《ALTERA FPGA/CPLD高级篇》高速DDR存储器数据接口设计实例- ALTERA FPGA/CPLD High chapter high-speed DDR memory data interface design example
Platform: |
Size: 24576 |
Author: shicheng342 |
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Description: davincievm 6446 記憶體DDR撿測-davincievm 6446 seized DDR memory test
Platform: |
Size: 48128 |
Author: 謝震威 |
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Description: 这是一个利用xilinx的macroblaze将用户程序由flash读取至ddr内存的例程，关键是bootloader的写法。-This is a use of Xilinx macroblaze the user program will read from flash memory to ddr routine, the key is the wording of bootloader.
Platform: |
Size: 1334272 |
Author: weichengguanzhe |
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Description: 用allegro画的ddr存储器电路。六层板设计，很好的参考资料-Allegro painting with ddr memory circuit. Six-storey plate design, very good reference
Platform: |
Size: 372736 |
Author: 朱宝军 |
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Description: 高速DDR存储器数据接口设计实例.
1. 将文件拷入硬盘
2. 产生DQS模块
3. 产生DQ模块
4. 产生PLL模块
5. 拷贝以上步骤生成的文件到子目录【Project】中
6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块
7. 编译并查看编译结果
-High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS generated module 3. Have a DQ module 4. Have a PLL module 5. Copies of the above steps to generate a document to a subdirectory 【Project】 6. Open the subdirectory 【Project】 DataPath.qpf in engineering, design top-level module 7. compilers to compile the results and see
Platform: |
Size: 28672 |
Author: 田文军 |
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Description: dsp 2812 mem 测试程序 用于对ddr进行初始化实现内存读写，在ccs下开发-dsp 2812 mem test program is used to initialize achieve ddr memory, reading and writing, developed under the ccs
Platform: |
Size: 159744 |
Author: SADFD |
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Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing
Warfare and Xilinx solutions, but also explains how to use Xilinx
Software tools and hardware-proven reference designs to be for your own
With (from low-cost DDR SDRAM applications to such as 667 Mb/s
This higher performance DDR2 SDRAM interface) design a complete deposit
Storage device interface solution.
Platform: |
Size: 1123328 |
Author: 陈阳 |
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Description: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Platform: |
Size: 52224 |
Author: yanxp |
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Description: 合众达DM6446试验箱学习实验源代码 ddr内存实验-the experimental source code DM6446 chamber ddr memory test
Platform: |
Size: 71680 |
Author: Daniel |
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Description: DDR内存条的设计资料，PC1600 and PC 21-DDR memory design data, PC1600 and PC 2100
Platform: |
Size: 340992 |
Author: minyi |
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Description: ddr memory design basics intro
Platform: |
Size: 304128 |
Author: Umapathi Nadendla |
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Description: 很好的PC内存条设计资料，如果你是内存设计的初学者，这里的资料很适合你，值得参考(Very good PC memory design information, if you are a beginner of memory design, the information here is very suitable for you, it is worth reference)
Platform: |
Size: 10548224 |
Author: armyzhang
|
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